Self-aligned extension junction for reduced gate channel
US6204133A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2000 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | Jun 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2255
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device having self-aligned extension junctions and a reduced gate channel length by etching an opening in a layer of phosphoro silicate glass that has been deposited on a substrate. The layer of phosphoro silicate glass serves as a self-aligned solid diffusion source to form LDD extensions. Spacers are formed on the walls of the opening in the phosphoro silicate glass and serve to reduce the length of the gate channel. A gate structure is formed by depositing a layer of gate oxide in the opening in the layer of phosphoro silicate glass and a layer of polysilicon is formed over the layer of gate oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.