Contact and deep trench patterning
US6204187A · kind A · utility
14Cited by
7References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 6, 1999 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | Jan 6, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for patterning semiconductor components includes the steps of providing a substrate layer, the substrate layer having a dielectric layer formed thereon and a mask layer formed on the dielectric layer, the mask layer being selectively etchable relative to the dielectric layer, patterning the mask layer to form a first group of substantially parallel lines in the mask layer and patterning the dielectric layer to form rectangular holes therein down to the substrate layer. A semiconductor device in accordance with the invention is also included.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.