Modified poly-buffered isolation
US6204547A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 22, 1999 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | Jun 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming field isolation regions (300) on a semiconductor substrate for an integrated circuit. The present method includes forming a sandwich type structure as an oxidation mask (140), (160), and (200). The present sandwich type structure includes an underlying oxide layer (120) formed overlying the top surface. The present sandwich type structure includes a polysilicon layer (140) overlying the oxide layer (120), a first silicon nitride layer (160) overlying the polysilicon layer (140), and a second silicon nitride layer (200) overlying the first silicon nitride layer (160) where the second silicon nitride layer (200) is much thicker than the first layer of silicon nitride (160). The present method also includes patterning the second silicon nitride layer (200), the first silicon nitride layer (160), and the polysilicon layer (140) to define an oxidation mask. The oxidation mask includes exposed regions (210) of the oxide layer (120) where field isolation oxide regions (300) will be formed therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.