Ball grid assembly type semiconductor package having improved chip edge support to prevent chip cracking
US6204559A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 1999 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | Nov 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention moves at least one outer via outwardly to a location under the edge of the chip so as to form an offset via. Since the via is made of copper, the offset via provides sufficient supporting strength for the chip edge during molding process. Further, this invention also disposes a copper mesh on the substrate at the area without vias and traces so as to enhance the substrate strength for supporting the chip. According to another aspect of this invention, dummy via holes are provided for the substrate at the area under the chip edge for supporting the chip. Since the copper mesh, offset via, the dummy via hole are made of copper having sufficient supporting strength for the chip, the crack problem during molding process can be eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.