Isolation collar nitride liner for DRAM process improvement

US6207494A · kind A · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Christoff Graimann · Villach, AT
• Angelika Schulz · Radeberg, DE
• Carlos Mazure · Austin, US
• Christian Dieseldorff · Austin, US

Key dates

• Filing date: Mar 31, 1999
• Grant date: Mar 27, 2001
• Expiry date: Mar 31, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/0385

Abstract

A method of fabricating a trench cell capacitor can be used in the formation of a DRAM cell. In one embodiment, a trench is formed within a semiconductor substrate. The trench is lined with a dielectric layer, e.g., an ONO layer. After lining the trench, a collar is formed in an upper portion of the trench by forming an oxide layer in the upper portion. A nitride layer on the oxide layer. The trench is then filled with semiconductor material. For example, a semiconductor region can be epitaxially grown to fill the trench.