Barrier applications for aluminum planarization
US6207558A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1999 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Oct 21, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides an effective barrier layer for improved via fill in high aspect ratio sub-micron apertures at low temperature, particularly at the contact level on a substrate. In one aspect of the invention, a feature is filled by first depositing a barrier layer onto a substrate having high aspect ratio contacts or vias formed thereon. The barrier layer is preferably comprised of Ta, TaN.sub.x, W, WN.sub.x, or combinations thereof. A CVD conformal metal layer is then deposited over the barrier layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal layer is deposited onto the previously formed CVD conformal metal layer at a temperature below that of the melting point temperature of the metal to allow flow of the CVD conformal layer and the PVD metal layer into the vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.