Integrated process for ashing resist and treating silicon after masked spacer etch
US6207565A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2000 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Jan 13, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31138
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for preparing a semiconductor substrate for subsequent silicide formation. In one embodiment, the present invention subjects the semiconductor substrate to an ashing environment. In the present embodiment, the ashing environment is comprised of H.sub.2 O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas. In so doing, contaminants on the semiconductor substrate are removed. Next, the present invention subjects a mask covering a polysilicon stack to a mask-removal ashing environment. In the present embodiment, the mask-removal ashing environment is comprised of an O.sub.2 plasma. In so doing, the mask covering the polysilicon stack is removed. As a result, the semiconductor substrate and the top surface of the polysilicon stack are prepared for subsequent silicide formation thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.