Oxide/nitride stacked gate dielectric and associated methods
US6207586A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 1999 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Jun 17, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02274
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making an oxide/nitride stacked layer makes the nitride layer defective so that it is semi-transparent or permeable to oxygen. The method includes first forming an oxide layer on a semiconductor substrate. The defective nitride layer is formed on the oxide layer using direct plasma enhanced chemical vapor deposition. The defective nitride layer is formed while exposing the plasma with a low energy magnetic field for providing a uniform energy distribution across a surface of the oxide layer. A resulting distribution of thicknesses of the defective nitride layer has a standard deviation less than about 1.5% across a wafer. The defective nitride layer is permeable to oxygen so that when the semiconductor substrate is annealed, the interface trap sites are significantly reduced or eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.