Circuit and method for refreshing data stored in a memory cell
US6208577A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 16, 1999 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Apr 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An IC includes a memory array that has memory cells for storing data and that refreshes the data stored in a memory cell during a respective refresh cycle of a refresh mode. The integrated circuit also includes a refresh circuit that during a first portion of the refresh mode implements a first series of refresh cycles in the memory array at a first frequency and that during a second portion of the refresh mode implements a second series of refresh cycles in the memory array at a second frequency. Such a refresh circuit allows longer internal row-line on times during a self-refresh mode without affecting the auto-refresh TRC, which is the specified maximum time that the IC requires to execute an auto-refresh cycle. Therefore, the IC can consume less power during a self-refresh mode and still meet the same auto-refresh specification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.