Processor having selectable exception handling modes
US6209083A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1997 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Oct 1, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An FPU configured to operate in normal and fast modes. In normal mode, floating point instructions are stalled in an address calculation unit of the processor until the previously issued floating point instruction has cleared the FPU, thereby indicating that the previous floating point instruction will not have an exception. In fast mode, the address calculation unit will issue a next floating point instruction to the FPU, where it is held in a 4-deep instruction queue, regardless of whether a prior instruction has cleared. By eliminating stalls in the instruction execution pipeline caused by floating point instructions being held in the address calculation unit pending clearance of the prior floating point instruction, the instruction execution pipeline may issue floating point instructions to the FPU at a faster rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.