Self-aligned eetching process
US6211091A · kind A · utility
10Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1999 |
| Grant date | Apr 3, 2001 |
| Priority date | — |
| Expiry date | Aug 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/712
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention describes a self-aligned etching process. A conductive layer and a first insulating layer are formed on a substrate in sequence, and then the conductive layer and the first insulating layer are patterned to form a plurality of stacks on desired regions. Subsequently, spacers are formed on sidewalls of each stack, and a stop layer is then formed on the substrate. A second insulating layer is formed on the substrate and is planarized. Portions of the second insulating layer are removed to form a plurality of openings and to expose portions of the stop layer located between spacers. The exposed stop layer is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.