Semiconductor memory array with buried drain lines and processing methods therefor
US6211547A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 1997 |
| Grant date | Apr 3, 2001 |
| Priority date | — |
| Expiry date | Nov 24, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory array and methods therefor is provided herein comprising a substrate; a plurality of memory cell field effect transistors formed on said substrate and being arranged thereon into rows and columns of transistors, each transistor includes a channel region interposed between drain and source regions, and overlaid by a control gate region; a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns; a plurality of second diffused elongated regions formed within said substrate that electrically connect in common the source regions of transistors in respective columns; and a plurality of elongated conductive line formed over said substrate that electrically connect in common the control gate regions of transistors in respective rows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.