Semiconductor package with wire protection and method therefor
US6211574A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 1999 |
| Grant date | Apr 3, 2001 |
| Priority date | — |
| Expiry date | Apr 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3862
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a semiconductor die mounted on an upper surface of a substrate. A number of wire bonds electrically connect between a number of bonding pads on the upper surface of the substrate and a number of bonding pads on an upper surface of the semiconductor die. A fixing portion surrounds the semiconductor die and covers a mediate portion of each wire bond. Encapsulating material is molded over the semiconductor die and the wire bonds to form an encapsulant. In an alternative embodiment, the fixing portion is provided on the upper surface of the substrate adjacent to a mold gate of the substrate where the wire sweeping is most likely to occur while molding. The fixing portion does not cover the semiconductor die to avoid thermal strain acting on the semiconductor die due to the different coefficients of thermal expansion between the fixing portion and the encapsulant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.