Method of manufacturing a plurality of semiconductor packages
US6214640A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 1999 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | Aug 3, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a plurality of semiconductor chips packages and the resulting chip package assemblies. The method includes providing a circuitized substrate having terminals and leads. A spacer layer is deposited or attached to the substrate and each chip is then attached to the spacer layer. Typically, the spacer layer is comprised of a compliant or resilient material. The terminals and leads are interconnected using leads, at least some of which are fan-out leads. A ring-like pattern of a curable composition is disposed around each chip and cured to form a support structure. The assembly is encapsulated by dispensing a composition which is curable to an encapsulant into the gaps between the support structures and the chips. The encapsulant material is then cured thereby defining a composite of chip assemblies which may be singulated into individual chip packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.