Method for manufacturing two-bit flash memory
US6214672A · kind A · utility
Assignees
Inventor
Key dates
| Filing date | Oct 28, 1999 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | Oct 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/691
Abstract
A method of manufacturing a two-bit flash memory. A substrate has a thin oxide layer, a silicon nitride layer and a material layer formed thereon in sequence. An opening is formed in the material layer and the silicon nitride layer to expose a portion of the thin oxide layer. A source/drain region is formed in the substrate beneath the portion of the thin oxide layer exposed by the opening. A first dielectric layer is formed in the opening. A portion of the material layer and a portion of the silicon nitride layer are removed to form a spacer on the sidewall of the first dielectric layer. The remaining material layer is removed. A portion of the thin oxide layer exposed by the remaining silicon nitride layer and the first dielectric layer is removed. A second dielectric layer is formed on a portion of the substrate exposed by the remaining thin oxide layer. A control gate is formed over the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.