Process of making densely patterned silicon-on-insulator (SOI) region on a wafer
US6214694A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 1998 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | Nov 17, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for making a SOI region and a bulk region in a semiconductor device. The process includes providing a SOI structure. The SOI structure has a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer. Next, a nitride layer is deposited on top of the SOI structure. The SOI structure is exposed by selectively etching portions of the nitride layer. The portion of the nitride layer which is not etched forms the SOI region. The silicon substrate is exposed by selectively etching the remaining portion of the exposed SOI structure. An epitaxial layer is grown in top of the exposed silicon substrate to form the bulk region. The nitride portion above the SOI structure is finally removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.