Method of implementing air-gap technology for low capacitance ILD in the damascene scheme
US6214719A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 1999 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | Sep 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Air-gap technology is introduced in the damascene scheme, reducing the capacitance between interconnect metal lines on an integrated circuit substrate, and ultimately enhancing the speed of the device. Reduction of extraneous signal energy (cross-talk) from traversing from one metal line to another is also realized. The method for implementing an air-gap filled dielectric between the interconnect metal lines involves depositing a first dielectric layer on the substrate at a predetermined height. Next the first dielectric is patterned and etched to form lines. A second dielectric layer is then deposited using air-gap technology, such that the second dielectric contains air-gaps between the first dielectric lines. These air-gaps are situated below the predetermined height of the first dielectric. The substrate is then polished so that the top surface of the first dielectric is exposed. The first dielectric lines are then etched and removed. A metal is deposited in place of the removed first dielectric lines, forming interconnect metal lines on the substrate having an air-gap filled dielectric therebetween. The air-gap filled dielectric has a dielectric constant on the order of k=1.9 …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.