Borderless contact to diffusion with respect to gate conductor and methods for fabricating
US6215190A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 1998 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | May 12, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.