Programmable logic device architecture with super-regions having logic regions and a memory region
US6215326A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 1999 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | Mar 10, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.