Semiconductor device testing and burn-in methodology
US6218202A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 1998 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Oct 6, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15331
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged semiconductor device and a method for burn-in and testing are disclosed. The package comprises a carrier having a pattern of contact pads for electrical connection, and also a pattern of testing pads for electrical characterization such that their location, size and composition allows a conversion to contact pads after the device has been electrically characterized following burn-in. Furthermore, an adapter and a method for burn-in and testing are disclosed for use in testing a variety of different semiconductor devices. The adapter comprises a carrier having a pattern of testing pads bordering the carrier outline, and routing strips which are structured such that the carrier is adaptable to the package of the device being tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.