Dual gate and double poly capacitor analog process integration

US6218234A · kind A · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Xing Yu · Singapore, SG
• Shao Kai · Shanghai, CN

Key dates

• Filing date: Apr 26, 1999
• Grant date: Apr 17, 2001
• Expiry date: Apr 26, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/811

Abstract

A method for integrating the dual gate and double poly capacitor processes to fabricate an analog capacitor integrated circuit device is described. An isolation region is provided separating a first active area from a second active area in a semiconductor substrate. A first gate oxide layer is formed overlying the semiconductor substrate in both active areas. A first polysilicon layer is deposited overlying the first gate oxide layer and the isolation region. An capacitor dielectric layer comprising an oxide layer and a nitride layer is deposited overlying the first polysilicon layer. The capacitor dielectric layer and first polysilicon layer are etched away where they are not covered by a mask to form a first polysilicon gate electrode in the first area and a polysilicon capacitor bottom plate and overlying capacitor dielectric overlying the isolation region. The first gate oxide layer is removed in the second area and a thinner second gate oxide layer is formed in the second area. A second polysilicon layer is deposited overlying the second gate oxide layer, bottom capacitor plate and capacitor dielectric, and the first polysilicon gate electrode. The second polysilicon layer is …