Memory cell sense amplifier
US6219290A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 1998 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Oct 14, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sensing circuit for sensing the logic state of a memory cell which minimizes read times is described which includes a first circuit branch corresponding to an array circuit path and a second circuit branch corresponding to a reference cell circuit path. In operation during the pre-decode interval, additional load and current generation circuitry are enabled in the first circuit path so that the voltage as seen by the sensing input of a sensing circuit comparator is driven to be essentially equivalent to that of the reference signal as established by the reference cell circuit path on the reference input of the sensing circuit comparator. Once the address has been decoded, the additional load circuitry is disabled so as to allow the sensing input of the comparator to transition to a voltage representative of the logic state stored in the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.