Method to trap air at the silicon substrate for improving the quality factor of RF inductors in CMOS technology
US6221727A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 1999 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Aug 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new method of fabricating an inductor utilizing air as an underlying barrier in the manufacturing of integrated circuits is described. A field oxide region is formed in and on a semiconductor substrate and then removed whereby a well is left in the semiconductor substrate. A polish stop layer is deposited over the substrate and within the well. The polish stop layer is covered and the well filled with a spin-on-glass layer. The spin-on-glass layer is polished back to the polish stop layer. The said polish stop layer is removed. A first oxide layer is deposited overlying the spin-on-glass layer and the semiconductor substrate and is patterned using an inductor reticle whereby a plurality of openings are made through the first oxide layer to the spin-on-glass layer. All of the spin-on-glass layer within the well is removed through the plurality of openings. Thereafter, a second oxide layer is deposited overlying the first oxide layer and capping the plurality of openings thereby forming an air barrier within the well. A metal layer is deposited overlying the second oxide layer and patterned using the same inductor reticle to form the inductor in the fabrication of an integrated cir…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.