Chip-on-chip interconnections of varied characteristics
US6225699A · kind A · utility
51Cited by
13References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1998 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | Jun 26, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1532
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Chip-on-chip interconnections of varied characteristics, such as varied diameters, heights and/or composition, are disclosed. A first chip-on-chip interconnection on a joining plane has a first characteristic (e.g., a first height) and a second chip-on-chip interconnection on the same joining plane has a second characteristic (e.g., a second height greater than the first height). The first and second characteristics of the chip-on-chip interconnections allow for chip-on-chip connections to other packages, substrates or chips of different levels and/or compositions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.