Modifying a design layer of an integrated circuit using overlying and underlying design layers
US6226781A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1998 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | Aug 12, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A computer-implemented method is provided in which a design layer of an integrated circuit is altered by spatial definition using underlying and overlying design layers. That is, the specific layers of an integrated circuit that impact the layer being modified are taken into account. According to an embodiment, the computer-implemented method is performed using, e.g., a CAD program. First, an original layout design comprising a plurality of design layers representing respective levels of an integrated circuit is generated. The targeted properties, e.g., electrical properties, of features in one design layer are determined based upon the arrangement of features in other design layers relative to the features in that one design layer. The features in the design layer being modified are then separated into different working layers such that each working layer includes features having at least one common targeted property. The features in each working layer may then be separately modified based upon the mutual targeted property of that working layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.