Method of making dual damascene conductive interconnections and integrated circuit device comprising same
US6228758A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 1998 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Oct 14, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1031
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming conductive interconnections on an integrated circuit device and an integrated circuit device comprising the same is disclosed. The method is comprised of forming first and second layers of dielectric materials that are selectively etchable with respect to one another. The method also comprises forming the second layer above the first layer and in a previously defined opening in the first layer. The method further comprises removing portions of the second layer to define an opening therein and to remove the portion of the second layer previously deposited in the opening in the first layer. Thereafter, a conductive material is positioned in both of the openings in the first and second layers. The integrated circuit device is comprised of first and second layers of dielectric material having openings formed therein and an integrally formed conductive structure formed only in the openings in the first and second layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.