Inventor · Radebeul, DE

Thomas Werner

61Patents
9h-index
58Co-inventors
81Inventor score

Filing activity: Aug 31, 1982 → Jul 25, 2016

Most-cited inventions

PatentTitleAreaCited byStatus
US6228758A Method of making dual damascene conductive interconnections and integrated circuit device comprising same Electricity 232 Expired
US8048811B2 Method for patterning a metallization layer by reducing resist strip induced damage of the dielectric material Electricity 152 Active
US5976948A Process for forming an isolation region with trench cap Emerging Cross-Sectional Technologies 27 Expired
US7085300B2 Integral vertical cavity surface emitting laser and power monitor Electricity 24 Expired
US6964874B2 Void formation monitoring in a damascene process Electricity 23 Expired
US4454495A Layered ultra-thin coherent structures used as electrical resistors having low temperature coefficient of resistivity Emerging Cross-Sectional Technologies 21 Expired
US6893956B2 Barrier layer for a copper metallization layer including a low-k dielectric Electricity 12 Expired
US7902581B2 Semiconductor device comprising a contact structure based on copper and tungsten Electricity 12 Active
US8344474B2 Microstructure device including a metallization structure with self-aligned air gaps and refilled air gap exclusion zones Electricity 11 Active
US6724096B2 Die corner alignment structure Emerging Cross-Sectional Technologies 9 Expired
US8048796B2 Microstructure device including a metallization structure with self-aligned air gaps formed based on a sacrificial material Electricity 8 Active
US7932166B2 Field effect transistor having a stressed contact etch stop layer with reduced conformality Electricity 7 Active
US7977237B2 Fabricating vias of different size of a semiconductor device by splitting the via patterning process Electricity 7 Active
US7022602B2 Nitrogen-enriched low-k barrier layer for a copper metallization layer Electricity 7 Expired
US7800106B2 Test structure for OPC-related shorts between lines in a semiconductor device Electricity 7 Active
US8399352B2 Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions Electricity 6 Active
US8679924B2 Self-aligned multiple gate transistor formed on a bulk substrate Electricity 6 Active
US7622391B2 Method of forming an electrically conductive line in an integrated circuit Electricity 6 Active
US8357610B2 Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectrics Electricity 5 Active
US7764078B2 Test structure for monitoring leakage currents in a metallization layer Electricity 5 Active
US8080866B2 3-D integrated semiconductor device comprising intermediate heat spreading capabilities Electricity 5 Active
US9455232B2 Semiconductor structure including a die seal leakage detection material, method for the formation thereof and method including a test of a semiconductor structure Electricity 3 Active
US7705352B2 Test structure for estimating electromigration effects with increased robustness with respect to barrier defects in vias Electricity 3 Active
US8609524B2 Method for making semiconductor device comprising replacement gate electrode structures with an enhanced diffusion barrier Electricity 3 Active
US8420533B2 Metallization system of a semiconductor device comprising rounded interconnects formed by hard mask rounding Electricity 3 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.