Memory cell configuration, method for fabricating it and methods for operating it

US6229169A · kind A · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Franz Hofmann · Munich, DE
• Wolfgang Krautschneider · Ottobrunn, DE
• Wolfgang Rosner · Hersbruck, DE
• Lothar Risch · Neubiberg, DE
• Till Schlosser · Dresden, DE
• Paul-Werner Basse · Wolfratshausen, DE

Key dates

• Filing date: Dec 17, 1998
• Grant date: May 8, 2001
• Expiry date: Dec 17, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A memory cell configuration contains a multiplicity of memory cells in a semiconductor substrate. Each of the memory cells has a selection transistor connected between a bit line and a storage element. The memory cells can each be driven via a first word line and a second word line, the first word line and the second word line crossing one another. The memory cell configuration is, in particular, a DRAM configuration.