Bitline latch switching circuit for floating gate memory device requiring zero volt programming voltage
US6233177A · kind A · utility
22Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2000 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Jun 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating gate memory device that includes a column latch circuit that is isolated from a series of bitlines by PMOS pass transistors controlled by a bitline latch switch circuit. The bitline latch switch circuit selectively applies either +5 V or -2 V signals to the gate terminals of the PMOS pass transistors, thereby allowing the PMOS pass transistors to selectively pass 0 (zero) Volts during, for example, program operations. A -2 V charge pump is activated to generate the -2 V signal during operations requiring 0 Volt bitline voltages, and is turned off during all other operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.