Built-in self test method for measuring clock to out delays
US6233205A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 1998 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Jul 14, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318516
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the period of the oscillator. The period of the oscillator is then related to the average signal propagation delay through the test circuit. The invention can be applied to synchronous components that might fail to oscillate by connecting the asynchronous set or clear terminal to the output terminal so that the oscillator oscillates at a frequency determined by the clock-to-out delay of those components. The configuration can thus be used to characterize synchronous and asynchronous components to provide data for predicting the timing behavior of circuits that include those or similar components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.