Method of improving parallelism of a die to package using a modified lead frame
US6235556A · kind A · utility
3Cited by
11References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 4, 1998 |
| Grant date | May 22, 2001 |
| Priority date | — |
| Expiry date | Sep 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and method are provided to allow a die to be packaged more uniformly and in parallel with a package by utilizing a lead frame having at least one cavity within the lead frame, thereby allowing excess die-attach epoxy can flow into the cavity or cavities and reducing the amount of contact surface area between the die and lead frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.