Method to form gate oxides of different thicknesses on a silicon substrate

US6235591A · kind A · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Narayanan Balasubramanian · Singapore, SG
• Yelehanka Ramachandamurthy Pradeep · Singapore, SG
• Jia Zhen Zheng · Singapore, SG
• Alan Cuthbertson · San Jose, US

Key dates

• Filing date: Oct 25, 1999
• Grant date: May 22, 2001
• Expiry date: Oct 25, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0144

Abstract

A method of fabricating gate oxides of different thicknesses has been achieved. Active area isolations are provided in a silicon substrate to define low voltage sections and high voltage sections in the silicon substrate. A sacrificial oxide layer is formed overlying the silicon substrate. A silicon nitride layer is deposited overlying the sacrificial oxide layer. A masking oxide layer is deposited overlying the silicon nitride layer. The masking oxide layer is patterned to form a hard mask overlying the low voltage sections. The silicon nitride layer is etched through where exposed by the hard mask thereby exposing the sacrificial oxide layer overlying the high voltage section. The exposed sacrificial oxide layer and the hard mask are etched away. A thick gate oxide layer is grown overlying the silicon substrate in the high voltage section. The silicon nitride layer is etched away. The sacrificial oxide layer overlying the low voltage section is etched away. A thin gate oxide layer is grown overlying the silicon substrate in the low voltage section, and the integrated circuit device is completed.