Method for forming isolation areas with improved isolation oxide

US6235609A · kind A · utility

Assignee

• Philips Electronics North America Corporation · US

Inventors

• Samit Sengupta · San Jose, US
• Faran Nouri · Los Altos, US

Key dates

• Filing date: Apr 3, 2000
• Grant date: May 22, 2001
• Expiry date: Apr 3, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76232
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

For use with a sub-micron semiconductor process, a trench isolation process enables the formation of a wider isolation oxide around the shallow trench isolation (STI) opening. The wider oxide width minimizes the recessing of oxide along the trench sidewalls during subsequent cleaning and etching steps. In a method for forming STI regions on a silicon substrate having a buffer oxide thereon and a nitride layer on top of the buffer oxide, a mask layer is defined on the nitride layer patterning isolation regions in unmasked areas of the nitride layer. Isolation regions of sufficient depth are etched through in unmasked areas of the nitride layer, the buffer oxide and into the silicon substrate. Performing a lateral etch (a nitride shaving) of the nitride layer under the mask layer undercuts a portion of the nitride layer under the mask layer. After the lateral etch, the mask layer is removed. The STI region is filled with an oxide layer and is planarized until the oxide layer is substantially flush with the nitride layer. The resulting oxide layer is wider and protects the STI region from subsequent processing.