Memory cell incorporating a chalcogenide element and method of making same
US6236059A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1997 |
| Grant date | May 22, 2001 |
| Priority date | — |
| Expiry date | Apr 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer process, small pores are formed in the silicon nitride to expose a portion of the polysilicon plugs. A chalcogenide material is disposed in the pores by depositing a layer of chalcogenide material on the silicon nitride layer and planarizing the chalcogenide layer to the silicon nitride layer using CMP. A layer of TiN is next deposited over the plugs, followed by a metallization layer. The TiN and metallization layers are then masked and etched to define memory cell areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.