Fernando Gonzalez
316Patents
48h-index
64Co-inventors
93Inventor score
Filing activity: Jan 9, 1989 → Apr 7, 2014
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6236059A | Memory cell incorporating a chalcogenide element and method of making same | Electricity | 428 | Expired |
| US5814527A | Method of making small pores defined by a disposable internal spacer for use in chalcogenide memories | Electricity | 408 | Expired |
| US5998244A | Memory cell incorporating a chalcogenide element and method of making same | Electricity | 361 | Expired |
| US5013680A | Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography | Emerging Cross-Sectional Technologies | 322 | Expired |
| US5841150A | Stack/trench diode for use with a muti-state material in a non-volatile memory cell | Electricity | 303 | Expired |
| US5970336A | Method of making memory cell incorporating a chalcogenide element | Electricity | 286 | Expired |
| US5831276A | Three-dimensional container diode for use with multi-state material in a non-volatile memory cell | Electricity | 286 | Expired |
| US6635552B1 | Methods of forming semiconductor constructions | Electricity | 284 | Expired |
| US5879955A | Method for fabricating an array of ultra-small pores for chalcogenide memory cells | Emerging Cross-Sectional Technologies | 283 | Expired |
| US6638834B2 | Methods of forming semiconductor constructions | Electricity | 273 | Expired |
| US6111264A | Small pores defined by a disposable internal spacer for use in chalcogenide memories | Electricity | 268 | Expired |
| US6153890A | Memory cell incorporating a chalcogenide element | Electricity | 266 | Expired |
| US6844243B1 | Methods of forming semiconductor constructions | Electricity | 256 | Expired |
| US5985698A | Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell | Electricity | 227 | Expired |
| US6104038A | Method for fabricating an array of ultra-small pores for chalcogenide memory cells | Emerging Cross-Sectional Technologies | 221 | Expired |
| US6927431B2 | Semiconductor circuit constructions | Electricity | 216 | Expired |
| US6376284B1 | Method of fabricating a memory device | Electricity | 215 | Expired |
| US6391688B1 | Method for fabricating an array of ultra-small pores for chalcogenide memory cells | Emerging Cross-Sectional Technologies | 198 | Expired |
| US6300684A | Method for fabricating an array of ultra-small pores for chalcogenide memory cells | Emerging Cross-Sectional Technologies | 192 | Expired |
| US5122848A | Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance | Electricity | 190 | Expired |
| US5250450A | Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance | Electricity | 147 | Expired |
| US6291276A | Cross coupled thin film transistors and static random access memory cell | Emerging Cross-Sectional Technologies | 110 | Expired |
| US5424993A | Programming method for the selective healing of over-erased cells on a flash erasable programmable read-only memory device | Physics | 107 | Expired |
| US5168073A | Method for fabricating storage node capacitor having tungsten and etched tin storage node capacitor plate | Electricity | 102 | Expired |
| US6383861B1 | Method of fabricating a dual gate dielectric | Electricity | 101 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.