Static timing analysis of digital electronic circuits using non-default constraints known as exceptions
US6237127A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 1998 |
| Grant date | May 22, 2001 |
| Priority date | — |
| Expiry date | Jun 8, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Exceptions allow a circuit designer, working with a circuit synthesis system, to specify certain paths through the circuit to be synthesized as being subject to non-default timing constraints. The additional information provided by the exceptions can allow the synthesis system to produce a more optimal circuit. A tag-based timing analysis tool is presented, which implements exceptions, and can be used in a synthesis system. A circuit is analyzed in "sections," which comprise a set of "launch" flip flops, non-cyclic combinational circuitry and a set of "capture" flip flops. The tag-based static timing analysis of the present invention is performed in four main steps: preprocessing, pin-labeling, RF timing table propagation and relative constraint analysis. Preprocessing converts the exceptions written by the circuit designer into a certain standard form in which paths through the circuit to be synthesized are expressed in terms of circuit "pins." Pin-labeling causes the particular circuit pins, which are the subject of exceptions, to be marked. During RF timing table propagation, "RF timing tables" with rise and fall times are propagated onto all pins of the circuit section. Rise an…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.