Method for constraining circuit element positions in structured layouts
US6237129A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 1998 |
| Grant date | May 22, 2001 |
| Priority date | — |
| Expiry date | Mar 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention supplies a method whereby placement information for elements of a logic module is specified in such a manner that specific coordinates need not be included. This method can be applied to any module or other element having an associated placement in a programmable device. Using the method of the invention, relative coordinates (such as the RLOC constraints discussed in relation to the prior art) need not be specified. Instead, the invention introduces a vector-based form of layout. Key words or phrases such as "COLUMN" or "ROW" indicate the manner in which the elements of the module are to be placed. Use of such parametric words or phrases removes from the module developer the burden of determining exactly how large the module will be for each parameter combination, and in some cases finding expressions by which the relative locations can be calculated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.