Ralph D. Wittig
56Patents
21h-index
68Co-inventors
91Inventor score
Filing activity: Dec 12, 1997 → Aug 31, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6091263A | Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM | Electricity | 318 | Expired |
| US6150838A | FPGA configurable logic block with multi-purpose logic/memory circuit | Electricity | 271 | Expired |
| US6150839A | Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM | Electricity | 167 | Expired |
| US6396302B2 | Configurable logic element with expander structures | Electricity | 89 | Expired |
| US6388466B1 | FPGA logic element with variable-length shift register capability | Electricity | 74 | Expired |
| US6118300A | Method for implementing large multiplexers with FPGA lookup tables | Electricity | 73 | Expired |
| US6457164B1 | Hetergeneous method for determining module placement in FPGAs | Physics | 67 | Expired |
| US6292925A | Context-sensitive self implementing modules | Physics | 66 | Expired |
| US6216258A | FPGA modules parameterized by expressions | Physics | 66 | Expired |
| US6208163A | FPGA configurable logic block with multi-purpose logic/memory circuit | Electricity | 65 | Expired |
| US6400180B2 | Configurable lookup table for programmable logic devices | Electricity | 58 | Expired |
| US6184712A | FPGA configurable logic block with multi-purpose logic/memory circuit | Electricity | 51 | Expired |
| US6260182A | Method for specifying routing in a logic module by direct module communication | Physics | 50 | Expired |
| US6243851A | Heterogeneous method for determining module placement in FPGAs | Physics | 49 | Expired |
| US9218443B1 | Heterogeneous multiprocessor program compilation targeting programmable integrated circuits | Physics | 42 | Active |
| US6501296B2 | Logic/memory circuit having a plurality of operating modes | Electricity | 38 | Expired |
| US6191610A | Method for implementing large multiplexers with FPGA lookup tables | Electricity | 33 | Expired |
| US6583645B1 | Field programmable optical arrays | Physics | 31 | Expired |
| US8443230B1 | Methods and systems with transaction-level lockstep | Physics | 31 | Active |
| US6237129A | Method for constraining circuit element positions in structured layouts | Physics | 21 | Expired |
| US7721090B1 | Event-driven simulation of IP using third party event-driven simulators | Physics | 21 | Active |
| US6505337B1 | Method for implementing large multiplexers with FPGA lookup tables | Electricity | 20 | Expired |
| US10747690B2 | Device with data processing engine array | Electricity | 19 | Active |
| US6353920B1 | Method for implementing wide gates and tristate buffers using FPGA carry logic | Physics | 16 | Expired |
| US8447957B1 | Coprocessor interface architecture and methods of operating the same | Physics | 15 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.