Method to reduce read gate disturb for flash EEPROM application
US6240016A · kind A · utility
40Cited by
5References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2000 |
| Grant date | May 29, 2001 |
| Priority date | — |
| Expiry date | Jan 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of reading a flash memory (EEPROM) device by applying zero volts to all bitlines and substrate terminal in the flash memory device, a positive voltage of between 4 to 5 volts is applied to the wordline to which the cell being read is attached and a voltage of less than equal to 2 volts is applied to the common source terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.