Method of bitline shielding in conjunction with a precharging scheme for nand-based flash memory devices
US6240020A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 1999 |
| Grant date | May 29, 2001 |
| Priority date | — |
| Expiry date | Oct 25, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory device includes an array of core cell blocks and page buffers with supporting input/output circuitry. The flash memory device, in addition, contains a method for shielding the bitline for a precharging scheme in which the bitline line of each page buffer is charged prior to the sensing/evaluation cycle of a particular memory element in each core cell block. The precharging scheme increases the speed of response in retrieving information from each core cell block because the bitline line is charged to a predetermined voltage prior to accessing the bitline. The bitline shielding method increases the speed of response further by shielding the effects of neighboring bitlines from each other during the evaluation cycle. The shielding method includes charging different bitlines to preset voltages and then maintaining the preset voltages on a set of the bitlines over the evaluation cycle. The preset voltages are maintained on those bitlines not connected with memory elements undergoing evaluation. The shielding method also includes grounding a latch contained in page buffers connected with the bitlines of memory elements undergoing evaluation prior to the evaluation cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.