Integrated edge exposure and hot/cool plate for a wafer track system
US6240874A · kind A · utility
12Cited by
2References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 27, 1999 |
| Grant date | Jun 5, 2001 |
| Priority date | — |
| Expiry date | May 27, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67103
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is provided an improved resist coating/developing processing method and apparatus for a wafer track system so as to increase its throughput. In a preferred embodiment, this is achieved by integrating a wafer edge exposure unit with a temperature control plate unit into a single integrated processing unit having the functionality of the two separate processing units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.