Circuit chip package and fabrication method

US6242282A · kind A · utility

Assignee

• General Electric Company · US

Inventors

• Raymond Albert Fillion · Niskayuna, US
• Ernest Wayne Balch · Malta, US
• Ronald Frank Kolc · Cherry Hill, US
• William Edward Burdick, Jr. · Niskayuna, US
• Robert J. Wojnarowski · Zion, US
• Leonard Richard Douglas · Burnt Hills, US
• Thomas Bert Gorczyca · Schenectady, US

Key dates

• Filing date: Oct 4, 1999
• Grant date: Jun 5, 2001
• Expiry date: Oct 4, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/19043
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad. In related embodiments vias are pre-metallized and coupled to chip pads of the circuit chips by an electrically conductive binder. Thin film passive components and multilayer interconnections can additionally be incorporated into the package.