Asic routing architecture

US6242767A · kind A · utility

Assignee

• Lightspeed Semiconductor Corporation · US

Inventors

• Dana How · Palo Alto, US
• Adi Srinivasan · Fremont, US
• Abbas El Gamal · Palo Alto, US

Key dates

• Filing date: Nov 10, 1997
• Grant date: Jun 5, 2001
• Expiry date: Nov 10, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/90

Abstract

A customizable ASIC routing architecture is provided. The architecture utilizes the uppermost metal layers of an ASIC composed of an array of function blocks for routing among function blocks while lower layers are used for local interconnections within the function blocks. The second-to-uppermost metal layer is fixed and generally includes a plurality of parallel segmented conductors extending in a first direction. The uppermost metal layer is customizable in a predesignated manner. Metal in the uppermost metal layer is selectively placed in tracks, which are substantially perpendicular to the segmented conductors in the layer below. Vias are provided between the two uppermost layers. One embodiment of the invention permits one-mask customization of an ASIC.