Memory architecture for non-volatile storage using gate breakdown structure in standard sub 0.35 micron process
US6243294A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2000 |
| Grant date | Jun 5, 2001 |
| Priority date | — |
| Expiry date | Apr 19, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A field programmable gate array (FPGA) contains an array of memory cells. A word line is coupled to a row of memory cells in the array. A second signal line is coupled to the row of memory cells and extends in parallel with the word line. The second signal line applies a zero voltage to the memory cells when programming a memory cell in the row of memory cells. The second signal line applies a positive voltage to the memory cells when programming a memory cell outside the row of memory cells. Each memory cell is a one-time programmable non-volatile memory cell. Each memory cell includes a storage transistor and an access transistor coupled to one another. The memory cell can be programmed by selecting a word line and a bit line associated with the memory cell being programmed. A zero voltage is applied to a third signal line coupled to the memory cell and extending parallel to the word line. A programming voltage is applied to the selected bit line to program the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.