Low temperature process for fabricating layered superlattice materials and making electronic devices including same
US6245580A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 1999 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Jan 11, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02197
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A coating of liquid precursor containing a metal is applied to a first electrode, baked on a hot plate in oxygen ambient at a temperature not exceeding 300.degree. C. for five minutes, then RTP annealed at 675.degree. C. for 30 seconds. The coating is then annealed in oxygen or nitrogen ambient at 700.degree. C. for one hour to form a thin film of layered superlattice material with a thickness not exceeding 100 nm. A second electrode is applied to form a capacitor, and a second anneal is performed in oxygen or nitrogen ambient at a temperature not exceeding 700.degree. C. If the material is strontium bismuth tantalate, the precursor contains u mole-equivalents of strontium, v mole-equivalents of bismuth, and w mole-equivalents of tantalum, where 0.8.ltoreq.u.ltoreq.1.0, 2.0.ltoreq.v.ltoreq.2.3, and 1.9.ltoreq.w.ltoreq.2.1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.