Method of formation of pseudo-SOI structures with direct contact of transistor body to the substrate
US6245636A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 20, 1999 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Oct 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76264
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for processing a semiconductor wafer transforms the wafer into one which has a plurality of surface semiconductor platforms for formation of integrated circuit elements thereupon. The platforms are connected to a subsurface bulk layer of semiconductor material via integrally-formed bridges of semiconductor material. The platforms are otherwise surrounded with an electrically-insulating material, thereby providing good insulation between adjacent of the platforms. The method includes the steps of placing a mask on a wafer surface of the wafer, forming a subsurface altered material beneath portions of the wafer surface not covered by the mask, creating exposure openings through the wafer surface to expose a portion of the subsurface altered material, selectively removing the subsurface altered material by selective etching, and filling the subsurface regions and the exposure openings with an electrically-insulating material. In an exemplary embodiment the mask includes a plurality of gate conductors. The wafer surface is bombarded with boron ions to create a subsurface boron-doped material, and the boron-doped material is removed using an appropriate selective etchant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.