Method for planarized deposition of a material
US6245655A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 1, 1999 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Apr 1, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7688
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for selective deposition of a material, such as copper, to form planarized inlaid device interconnect structures, the method suppressing deposition of the material at other than the defined interconnect inlaid metal line trenches and via plug holes. Once a formation is filled with metallization material, deposition is automatically ceased in situ to form a globally planarized interconnect structure. In one embodiment, a blocking agent layer inhibits material nucleation and deposition at the substrate surface plane until the formation is filled, and then flows over the filled inlaid metallization structure to cease further material deposition and to form a globally planarized surface without a need for chemical-mechanical polishing of the metallization material. In another embodiment, an enhancement agent is provided within formations to reduce material nucleation time, resulting in selective deposition of the material proximate to the enhancement agent layer within trenches and holes. A nucleation suppressing agent can be included in the deposition ambient to increase nucleation delay and to suppress material deposition over the patterned field regions and on the formation…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.