Power trench transistor device source region formation using silicon spacer

US6246090A · kind A · utility

Assignee

• Intersil Corporation · US

Inventors

• Linda S. Brush · Smethport, US
• Jun Zeng · Torrance, US
• John J. Hackenberg · West Melbourne, US
• Jack H. Linn · Melbourne, US
• George V. Rouse · Indialantic, US

Key dates

• Filing date: Mar 14, 2000
• Grant date: Jun 12, 2001
• Expiry date: Mar 14, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/256

Abstract

A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.