System and method for forming a uniform thin gate oxide layer
US6246095A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 1998 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Sep 3, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28211
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention includes a novel synthesis of a three-step process of growing, depositing and growing Si0.sub.2 under low pressure, e.g., 0.2-10 Torr, to generate high quality, robust and reliable gate oxides for sub 0.5 micron technologies. The first layer, 1.0-3.0 nm is thermally grown for passivation of the Si-semiconductor surface. The second deposited layer 1.0-5.0 nm forms an interface with the first grown layer. During the third step of the synthesis densification of the deposited oxide layers occurs with a simultaneous removal of the interface traps at the interface and growth of a stress-modulated Si0.sub.2 occurs at the Si/first grown layer interface in the presence of a stress-accommodating interface layer resulting in a planar and stress-reduced Si/SiO.sub.2 interface. The entire synthesis is done under low-pressure (e.g., 0.2-10 Torr) for slowing down the oxidation kinetics to achieve ultrathin sublayers and may be done in a single low-pressure furnace by clustering all three steps. For light nitrogen-incorporation (<5%) for certain devices, often required due to improved resistance to boron and other dopant diffusion and hot-carrier characteristics, N.sub.2 O or NO in …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.