Apparatus and method for using checking instructions in a floating-point execution unit
US6247117A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 8, 1999 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Mar 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30192
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The use of checking instructions to detect special and exceptional cases of a defined data format in a microprocessor is disclosed. Generally speaking, a checking instruction is included with the microcode of floating-point instructions to detect special and exceptional cases of operand values for the floating-point instructions. A checking instruction is configured to set one or more flags in a flags register if it detects a special or exceptional case for an operand value. A checking instruction may also set the result or results of a floating-point instruction to a result value if a special or exceptional case is detected. In addition, a checking instruction may be configured to set one or more bits in status register if a special or exceptional case is detected. After a checking instruction completes execution, a subsequent microcode instruction can be executed to determine if one or more flags were set by the checking instruction. If one or more flags have been set by the checking instruction, the subsequent microcode instruction can branch to a non-sequential microcode instruction to handle the special or exceptional case detected by the checking instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.